`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    20:20:48 08/08/2011 
// Design Name: 
// Module Name:    LEDglow 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module LEDglow(clk, LED);
input clk;
output LED;

reg [23:0] cnt = 24'b0;
always @(posedge clk) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];
reg [4:0] PWM = 4'b0;
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];
endmodule


module LEDglow(clk, LED);
input clk;
output LED;

reg [23:0] cnt = 24'b0;
always @(posedge clk) cnt<=cnt+1;

wire [3:0] PWM_input = cnt[23] ? cnt[22:19] : ~cnt[22:19];
reg [4:0] PWM = 4'b0;
always @(posedge clk) PWM <= PWM[3:0]+PWM_input;

assign LED = PWM[4];
endmodule